Low cost fast recovery diode and process of its manufacture

ABSTRACT

A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periphery of the oxide termination ring. Platinum atoms are diffused into the back surface of the device. A three mask process is described. An amorphous silicon layer is added in a four mask process, and a plurality of spaced guard rings are added in a five mask process.

RELATED APPLICATION

[0001] This application claims the benefit of U.S. ProvisionalApplication No. 60/280,972, filed Apr. 2, 2001.

FIELD OF THE INVENTION

[0002] This invention relates to semiconductor devices and processingand more specifically relates to a low cost process for the manufactureof a fast recovery diode and to a novel fast recovery diode structure.

BACKGROUND OF THE INVENTION

[0003] Fast recovery diodes are well known. The processes used for themanufacture of such devices frequently employ cellular and/or stripeand/or trench technologies in a silicon die with electron irradiationfor lifetime killing. Such devises use a high mask count and arerelatively expensive.

[0004] It would be desirable to make a fast recovery diode (FRED) with areduced mask count and lifetime killing but with equal or bettercharacteristics to those of existing FRED devices.

BRIEF DESCRIPTION OF THE INVENTION

[0005] In accordance with the invention a novel FRED is formed using asingle large area junction with platinum lifetime killing. A simplifiedtermination structure is employed using a simple field plate terminationat low voltages (200 volts); amorphous silicon on the field plate atintermediate voltage (400 volts); and plural floating guard rings and anequipotential ring in the cutting street in a higher voltage (600 volts)device. Three, four and five masks are used for the 200 volt, 400 voltand 600 volt devices respectively. Excellent characteristics, equivalentto or better than those of existing FREDs with higher mask counts, areobtained.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is a cross-section of a portion of a novel FRED die made inaccordance with the invention by a 3 mask process for a 200 volt device.

[0007]FIG. 2 is a cross-section of a portion of a novel FRED die made inaccordance with the invention by a 4 mask process for a 400 volt device.

[0008]FIG. 3 is a cross-section of a portion of a novel FRED device madein accordance with the invention by a 5 mask process for a 600 voltdevice.

DETAILED DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 shows, in cross-section, a portion of a fast recovery diodedie 50 and its termination. The diode consists of a simple large area Ptype diffusion 51 in an N type epitaxial layer 52 atop the die 50.Diffusion 51 is a boron diffusion having a depth of 6 μm and a peakconcentration of 2E19/cm³. A field oxide 54 is formed atop the siliconsurface and a conductive (aluminum) field plate 52 which is an extensionof the anode electrode is also formed. A metal (aluminum) EQR ring 53completes the termination. An anode contact is connected to the P typediffusion 51 over substantially the full top area of die 50 and acathode contact (not shown) is connected to its bottom surface. Platinumatoms are diffused into the back surface of the die (wafer) which aredriven in from a 10 Å thick layer of platinum for 30 minutes at 950° C.Note that the dimensions on FIG. 1 (and FIGS. 2 and 3) are out of scaleand are in microns.

[0010] The novel structure of FIG. 1 is made by the following novel 3mask process of the invention for a FRED rated at 200 volts. Thestarting wafer has an N⁺ arsenic doped substrate which has an N⁻phosphorus doped epitaxial layer 52. The epitaxial layer thickness is 25μm and has a resistivity of 10 ohm-cm. The process steps used are givenin the following Table: STEP NOTE Field Ox 54 Oxide grown to 1.4 umthick MASK 1 Oxide Etch BOE Etch; 17 minutes BBr3 Preclean Time out 2 hbefore a BBr3 dep BBr3 Dep Target sheet resistance 55 ohm/square BBr3Deglass 4 min etch in 50:1 H2O:HF, 15 min timeout after BBr3 Dep BBr3 Oxpreclean time out 2 h before BBr3 ox BBr3 Ox Target xj = 5 um POC13 depTarget sheet resistance 14.5 ohm square POC13 deglass Etch time 1 min.time out after POC13 dep 2 hrs. POC13 OX Dry oxidation. Oxide thickness100 A. MASK 2 (open active area and termination) Oxide Etch Etch time 15min Preclean 50:1 H2O:HF Pt. evap 10 Å on wafer back. Platinum drive in30 min at 950° C. Quick extraction. Preclean 50:1 H2O:HF Al/Si sputter(52) Al/Si sputtering, 3 um thickness MASK 3 Al etch 7 min in aluminumetch solution Defreckle 1 min in Ashland Defreckle solution PhotoresistStrip Standard process Al sinter 30 min, 420° C., Forming gasatmosphere. Wafer Tape Tape on wafer front Wafer backgrind 14 mil Waferdetape Standard process Backside metal CrNiAg sputtering. Test ProbeTest for 200 V FRED.

[0011]FIG. 2 shows a cross-section like that of FIG. 1, but with atermination modified to make the device a 400 volt device with a 4 maskprocess. Components similar to those of FIG. 1 have similar identifyingnumerals.

[0012] In order to withstand 400 volts, the device of FIG. 2 employs anadded diffusion defining termination P ring 60, an added field plate 61and an amorphous silicon layer 63 on top of the termination surface,including field plates 52 and 61 and EQR ring 53.

[0013] The device of FIG. 2 is made by a novel 4 mask process toincrease the device rating to 400 volts. The process begins with a waferlike that of FIG. 1, except that the epitaxial layer 52 is 47 μm thick,and has a resistivity of 15 ohm-cm.

[0014] The process for the devices of FIG. 2 starts with steps 1 to 22above up to (“photorest strip” and before “Al sinter”) for the device ofFIG. 1. Following step 22, and before Al sinter, a layer 63 of amorphoussilicon, 1 800 Å thick, is deposited atop the wafer surface. A mask 4step is then carried out to etch the amorphous silicon to open theactive area; specifically, a wet etch (DFK) process.

[0015]FIG. 3 is a cross-section like that of FIGS. 1 and 2 with elementsadded to permit the device to operate at 600 volts. The process used isa 5 mask process. The elements added are P diffusion rings 70 to 73 andN⁺ diffusion 74 in the cutting street and surrounding the die edge toact as an N⁺ EQR ring, and a modified metal EQR ring 75. The startingwafer for the 600 volt device has an epitaxial layer 52 thickness of 61μm and resistivity of 21.5 ohm-cm. The novel 5 mask process for makingthe device of FIG. 3 employs the steps used for the 400 volt device ofFIG. 2, except that a further mask step is used after step 8 above andfollowing the B Br Ox step. Following this added mask step, there is aBOE etch for 17 minutes to open windows for the guard ring diffusionsand the process continues as described for FIGS. 1 and 2.

[0016] In each of FIGS. 1, 2 and 3, the novel FRED device employs asingle large P diffusion for the active area and platinum atoms for lifetime killing. In FIGS. 2 and 3, the device termination is covered withamorphous silicon.

[0017] Although the present invention has been described in relation toparticular embodiments thereof, many other variations and modificationsand other uses will become apparent to those skilled in the art.

What is claimed is:
 1. A fast recovery diode comprising a silicon diehaving a substrate of a first conductivity type; a single centraldiffusion extending onto the upper surface of said die and of the otherconductivity type defining a single continuous P-N junction; atermination region surrounding the outer periphery of said upper surfaceof said device and including a silicon dioxide layer which overlies theouter edge of said diffusion and which defined the diffusion window forsaid single diffusion; an anode contact metal in contact with thesurface of said diffusion and overlying the inner peripheral edge ofsaid silicon dioxide layer to define a field plate; an EQR conductivering which is separated from said anode contact and which extends overthe outer peripheral edge of said silicon dioxide layer; and platinumatoms diffused into the back surface of said die to act as life timekillers.
 2. The diode of claim 1, which further includes at least onefloating guard ring diffusion disposed beneath and laterally adjacent tosaid filed plate.
 3. The diode of claim 1, which further includes anamorphous silicon layer deposited atop said termination region.
 4. Thediode of claim 2, which further includes an amorphous silicon layerdeposited atop said termination region.
 5. The diode of claim 4, whichfurther includes a further conductive field plate in said terminationdisposed between and spaced from said first named field plate and saidEQR ring, with said amorphous silicon layer overlying said first namedfield plate, said second field plate and said EQR ring.
 6. The diode ofclaim 5, which further includes a plurality of spaced floating guardring diffusions in said upper surface and between said first named fieldplate and said second field plate and a guard ring in the peripheraledge of said die.
 7. The device of claim 1, wherein said firstconductivity type is the N type.
 8. The device of claim 2 wherein saidfirst conductivity type is the N type.
 9. The device of claim 3, whereinsaid first conductivity type is the N type.
 10. The device of claim 5,wherein said first conductivity type is the N type.
 11. The device ofclaim 6, wherein said first conductivity type is the N type.
 12. Areduced mask process for forming a fast recovery diode comprising thesteps of forming a field oxide atop a silicon die; applying a first maskto said top surface of said field oxide and etching a large area windowin the center thereof and leaving an outer oxide termination ring;diffusing impurity atoms through said window to define a large area P/Njunction; applying a second mask to said surface and etching a windowtherein to clear said central area for the application of an anodecontact; evaporating platinum metal on the back surface of said die andheating said die to drive platinum atoms into said die; depositing metalatop said top surface of said die and to the top of the P/N junction andover the oxide termination ring; and applying a third mask to said topsurface and opening windows to etch said metal to define an anodecontact which overlies the inner periphery of said termination ring anda separate EQR ring which overlies the outer periphery of saidtermination ring.
 13. The process of claim 13, wherein said platinummetal has a thickness of about 10 Å and is driven at about 950° C. forabout 30 minutes.
 14. The process of claim 12, which includes thefurther step of depositing an amorphous silicon layer atop said diesurface, and a further mask step for removing said amorphous siliconfrom atop the active P/N junction area and leaving it atop and incontact with said field plate and said EQR ring.
 15. The process ofclaim 13, which includes the further step of depositing an amorphoussilicon layer atop said die surface, and a further mask step forclearing said amorphous silicon from atop the active P/N junction areaand leaving it atop and in contact with said field plate and said EQRring.
 16. The process of claim 14, which includes a further mask stepfor defining a plurality of spaced floating guard ring diffusions insaid upper surface of said die which are spaced between said field plateand an adjacent outer field plate.